Organic thin-film transistors (OTFTs)-based electronics performing simple operations offer unique attractions compared to conventional inorganic technology, including low-cost large-area coverage, and low processing temperatures suitable for flexible substrates. A typical OTFT includes a number of layers and can be configured in various ways. For example, a bottom-gate top-contact OTFT includes a substrate with a gate electrode thereon, a dielectric layer deposited over the gate electrode, a semiconductor layer in contact with the dielectric layer, and source and drain electrodes separated from each other and deposited on the semiconductor layer. In this device architecture, the current between the source electrode and the drain electrode is modulated by both the source-drain voltage (VSD) and the source-gate voltage (VG). When the device is in the off-state (VG=0V), the channel current is very low, whereas in the on-state of the source-gate voltage (VG≠0V), large current increase is observed. The saturation current in organic thin-film transistors is generally described by Equation 1
                                          I            DS                    =                                    W                              2                ⁢                L                                      ⁢            μ            ⁢                                                  ⁢                                                            C                  i                                ⁡                                  (                                                            V                      G                                        -                                          V                      T                                                        )                                            2                                      ,                            (        1        )            where, μ is the field-effect charge carrier mobility, Ci is the capacitance per unit area of the dielectric, VT is the threshold voltage, and W and L are the OTFT channel width and length, respectively. Despite recent impressive progress of new organic semiconductors, large OTFT operating voltages, reflecting the intrinsically low mobilities of organic semiconductors compared to conventional inorganic semiconductors, remain one of the major challenges to overcome. For low power applications such as RFID, displays, and portable electronics, it is mandatory to achieve high TFT drain currents (ISD) at acceptably low operating voltages. Without changing device geometry (W and L) and semiconductor material (μ), equivalent OTFT ISD can be achieved at lower operating voltages by increasing the gate dielectric capacitance Ci, given by Equation 2
                                          C            i                    =                                    ɛ              0                        ⁢                          k              d                                      ,                            (        2        )            where ∈0 is the vacuum permittivity, k is the dielectric constant, and d is the thickness of dielectric layer. From Equation 2, it can be seen that operating bias reduction can be achieved by increasing the dielectric constant (k) or decreasing the thickness (d) of the gate dielectric. An increase of the k/d ratio is also essential for efficient device scalability, a prerequisite to improving low-power TFT operation.
Gate electric materials that can be processed by solution and at low temperatures are important to enable compatibility with flexible plastic substrates. Crosslinked polymer films, inorganic metal oxides, polymer/high-k nanoparticle composites and hybrid organic/inorganic dielectrics have been investigated as candidates for low-voltage TFTs. However, many of these dielectrics have limitations in achieving practical applications for flexible low-voltage TFTs. For example, crosslinked polymer materials have relatively low-k values and thus TFT drain currents (ISD) at low operating voltages often are not sufficiently high. An alternative approach is to employ high-k materials such as metal oxide (MO) films. However, high-quality MO dielectric films often require high growth/annealing temperatures (>400° C.) or vacuum conditions (atomic layer or chemical/physical vapor deposition) to ensure low leakage currents. Furthermore, most high-k metal oxide materials, particularly crystalline metal oxide materials, are often too brittle for flexible applications. Another method to increase the k/d ratio and mechanical flexibility is to use polymer-high k inorganic nanoparticle composites. However, because the dielectric constant of these composite materials is dominated by the relatively low-k polymer component, a large nanoparticle load is necessary to increase the k value of the composite, resulting in increased surface roughness. Lastly, although hybrid gate dielectrics composed of self-assembled monolayers or multilayers on ultrathin inorganic oxides show promise for low-voltage OTFTs, their integration into large-volume coating processes can be difficult.
Therefore, there is a need in the art for dielectric materials that can be prepared at low temperatures via solution-phase processes and that can enable low-voltage TFTs.